Cadence Q DRIVE SERIES Instrukcja Użytkownika

Synthesis and Timing Verification TutorialByDr. Ahmet BindalComputer Engineering DepartmentSan Jose State University

C. OptimizationOne last thing you should experiment is to optimize your gate-level netlist to reduce thepropagation delay between the flip-flop bound

Appendix AVerilog RTL files:(a) The top level-module, my_design.v:module my_design (bypass0, bypass1, module_clock, rst, a, b, cin, sel, out_sum,out_c

(c) ff.v:module ff (clk, rst, d, q);input clk, rst, d;output q;reg q;always @(posedge clk)beginif(rst)q = 0;elseq = d;endendmodule(d) mux.v:module

Appendix BTo understand the timing report, first right-click on your mouse button when you are onthe schematic window. Select “worst path” to highlig

timing.rpt file:+--------------------------------------------+| Report | report_timing ||---------------------+----------------------|| Options | >

A. SynthesisThis tutorial introduces the basics of Cadence’s Synthesis and Timing Verification tool(Ambit BuildGates Synthesis), and how to obtain a

(ii) Prepare the “environment” template for Synthesis, “setup.tcl”Generate the setup.tcl file in “synthesis” directory.setup.tcl file:proc setup {} {

(c) Reading Verilog RTL files:In order to have Synthesis tool read your Verilog files go to the “ac_shell” window, andtype the following:ac_shell>

(f) Zoom in and out on the schematic:To zoom in, use the left mouse button, click and hold on the schematic and movedownward.You can also use the “zo

B. Timing Verification(i) Prepare the “timing verification” template for timing verification tool,“timing.tcl”You need to generate another template i

DQDQDQDQINPUT PORTS OUTPUT PORTSPrevious ModuleNext ModuleMy ModuleSet Input Delayto (tclkq+Tin)Set External Delayto (tsu+Tex)Previous Module must sup

(ii) Define the top-level module for timing verificationJust like what you have done for Synthesis you need to define the top-level module fortiming

As you can see this script generates a “report” and a “netlist” directory under“synthesis” directory. It subsequently forms 3 files, timing.rpt, area