Cadence M7000 Instrukcja Użytkownika

®Altera Corporation 1MAX 7000Programmable LogicDevice FamilyJune 2003, ver. 6.6 Data SheetDS-MAX7000-6.6Features... High-performance, EEPROM-based p

10 Altera CorporationMAX 7000 Programmable Logic Device Family Data SheetFigure4 shows a MAX 7000E and MAX 7000S device macrocell.Figure 4. MAX 7000E

Altera Corporation 11MAX 7000 Programmable Logic Device Family Data SheetEach programmable register can be clocked in three different modes: By a gl

12 Altera CorporationMAX 7000 Programmable Logic Device Family Data SheetShareable ExpandersEach LAB has 16 shareable expanders that can be viewed as

Altera Corporation 13MAX 7000 Programmable Logic Device Family Data SheetThe compiler can allocate up to three sets of up to five parallel expanders

14 Altera CorporationMAX 7000 Programmable Logic Device Family Data SheetProgrammable Interconnect ArrayLogic is routed between LABs via the programma

Altera Corporation 15MAX 7000 Programmable Logic Device Family Data SheetFigure 8. I/O Control Block of MAX 7000 DevicesNote:(1) The open-drain outpu

16 Altera CorporationMAX 7000 Programmable Logic Device Family Data SheetWhen the tri-state buffer control is connected to ground, the output istri-st

Altera Corporation 17MAX 7000 Programmable Logic Device Family Data SheetfFor more information on using the Jam language, see Application Note 88 (Us

18 Altera CorporationMAX 7000 Programmable Logic Device Family Data SheetProgramming TimesThe time required to implement each of the six programming s

Altera Corporation 19MAX 7000 Programmable Logic Device Family Data SheetThe programming times described in Tables 6 through 8 are associated with th

2 Altera CorporationMAX 7000 Programmable Logic Device Family Data Sheet...and More Features Open-drain output option in MAX 7000S devices Programma

20 Altera CorporationMAX 7000 Programmable Logic Device Family Data SheetProgrammable Speed/Power ControlMAX 7000 devices offer a power-saving mode th

Altera Corporation 21MAX 7000 Programmable Logic Device Family Data SheetBy using an external 5.0-V pull-up resistor, output pins on MAX 7000S device

22 Altera CorporationMAX 7000 Programmable Logic Device Family Data SheetIEEE Std. 1149.1 (JTAG) Boundary-Scan SupportMAX 7000 devices support JTAG BS

Altera Corporation 23MAX 7000 Programmable Logic Device Family Data SheetThe instruction register length of MAX 7000S devices is 10 bits. Tables 10 a

24 Altera CorporationMAX 7000 Programmable Logic Device Family Data SheetFigure9 shows the timing requirements for the JTAG signals.Figure 9. MAX 7000

Altera Corporation 25MAX 7000 Programmable Logic Device Family Data SheetDesign SecurityAll MAX 7000 devices contain a programmable security bit that

26 Altera CorporationMAX 7000 Programmable Logic Device Family Data SheetOperating ConditionsTables 13 through 18 provide information about absolute m

Altera Corporation 27MAX 7000 Programmable Logic Device Family Data SheetTable 15. MAX 7000 5.0-V Device DC Operating Conditions Note (9)Symbol Param

28 Altera CorporationMAX 7000 Programmable Logic Device Family Data SheetNotes to tables:(1) See the Operating Requirements for Altera Devices Data Sh

Altera Corporation 29MAX 7000 Programmable Logic Device Family Data SheetFigure 12. MAX 7000 Timing ModelNotes:(1) Only available in MAX 7000E and MA

Altera Corporation 3MAX 7000 Programmable Logic Device Family Data Sheet Additional design entry and simulation support provided by EDIF 2 0 0 and 3

30 Altera CorporationMAX 7000 Programmable Logic Device Family Data SheetFigure 13. Switching WaveformsCombinatorial ModeInput PinI/O PinPIA DelayShar

Altera Corporation 31MAX 7000 Programmable Logic Device Family Data SheetTables 19 through 26 show the MAX 7000 and MAX 7000E AC operating conditions

32 Altera CorporationMAX 7000 Programmable Logic Device Family Data SheetTable 20. MAX 7000 & MAX 7000E Internal Timing Parameters Note (1)Symbol

Altera Corporation 33MAX 7000 Programmable Logic Device Family Data SheetTable 21. MAX 7000 & MAX 7000E External Timing Parameters Note (1)Symbol

34 Altera CorporationMAX 7000 Programmable Logic Device Family Data SheetTable 22. MAX 7000 & MAX 7000E Internal Timing Parameters Note (1)Symbol

Altera Corporation 35MAX 7000 Programmable Logic Device Family Data SheetTable 23. MAX 7000 & MAX 7000E External Timing Parameters Note (1)Symbol

36 Altera CorporationMAX 7000 Programmable Logic Device Family Data SheetTable 24. MAX 7000 & MAX 7000E Internal Timing Parameters Note (1)Symbol

Altera Corporation 37MAX 7000 Programmable Logic Device Family Data SheetTable 25. MAX 7000 & MAX 7000E External Timing Parameters Note (1)Symbol

38 Altera CorporationMAX 7000 Programmable Logic Device Family Data SheetTable 26. MAX 7000 & MAX 7000E Internal Timing Parameters Note (1)Symbol

Altera Corporation 39MAX 7000 Programmable Logic Device Family Data SheetNotes to tables:(1) These values are specified under the recommended operati

4 Altera CorporationMAX 7000 Programmable Logic Device Family Data SheetThe MAX 7000E devices—including the EPM7128E, EPM7160E, EPM7192E, and EPM7256E

40 Altera CorporationMAX 7000 Programmable Logic Device Family Data SheetfACNTMaximum internal array clock frequency(4) 175.4 142.9 116.3 100.0 MHzfMA

Altera Corporation 41MAX 7000 Programmable Logic Device Family Data SheetNotes to tables:(1) These values are specified under the recommended operati

42 Altera CorporationMAX 7000 Programmable Logic Device Family Data SheettACO1Array clock to output delay C1 = 35 pF 5.4 6.7 7.5 10.0 nstACHArray cloc

Altera Corporation 43MAX 7000 Programmable Logic Device Family Data SheetNotes to tables:(1) These values are specified under the recommended operati

44 Altera CorporationMAX 7000 Programmable Logic Device Family Data SheetTables 31 and 32 show the EPM7128S AC operating conditions.Table 31. EPM7128S

Altera Corporation 45MAX 7000 Programmable Logic Device Family Data SheetTable 32. EPM7128S Internal Timing Parameters Note (1)Symbol Parameter Condi

46 Altera CorporationMAX 7000 Programmable Logic Device Family Data SheetNotes to tables:(1) These values are specified under the recommended operatin

Altera Corporation 47MAX 7000 Programmable Logic Device Family Data SheettACNTMinimum array clock period 6.7 8.2 10.0 13.0 nsfACNTMaximum internal ar

48 Altera CorporationMAX 7000 Programmable Logic Device Family Data SheetNotes to tables:(1) These values are specified under the recommended operatin

Altera Corporation 49MAX 7000 Programmable Logic Device Family Data SheettAHArray clock hold time 1.8 3.0 4.0 nstACO1Array clock to output delay C1 =

Altera Corporation 5MAX 7000 Programmable Logic Device Family Data SheetThe MAX 7000 architecture supports 100% TTL emulation and high-density integr

50 Altera CorporationMAX 7000 Programmable Logic Device Family Data SheetNotes to tables:(1) These values are specified under the recommended operatin

Altera Corporation 51MAX 7000 Programmable Logic Device Family Data SheetTables 37 and 38 show the EPM7256S AC operating conditions.Table 37. EPM7256

52 Altera CorporationMAX 7000 Programmable Logic Device Family Data SheetTable 38. EPM7256S Internal Timing Parameters Note (1)Symbol Parameter Condit

Altera Corporation 53MAX 7000 Programmable Logic Device Family Data SheetNotes to tables:(1) These values are specified under the recommended operati

54 Altera CorporationMAX 7000 Programmable Logic Device Family Data SheetThis calculation provides an ICC estimate based on typical conditions using a

Altera Corporation 55MAX 7000 Programmable Logic Device Family Data SheetFigure 14 shows typical supply current versus frequency for MAX7000 devices.

56 Altera CorporationMAX 7000 Programmable Logic Device Family Data SheetFigure 14. ICC vs. Frequency for MAX 7000 Devices (Part 2 of 2)VCC = 5.0 VRoo

Altera Corporation 57MAX 7000 Programmable Logic Device Family Data SheetFigure 15 shows typical supply current versus frequency for MAX 7000S device

58 Altera CorporationMAX 7000 Programmable Logic Device Family Data SheetFigure 15. ICC vs. Frequency for MAX 7000S Devices (Part 2 of 2)DevicePin-Out

Altera Corporation 59MAX 7000 Programmable Logic Device Family Data SheetFigures 16 through 22 show the package pin-out diagrams for MAX 7000 devices

6 Altera CorporationMAX 7000 Programmable Logic Device Family Data SheetMAX 7000 devices contain from 32 to 256 macrocells that are combined into grou

60 Altera CorporationMAX 7000 Programmable Logic Device Family Data SheetFigure 17. 68-Pin Package Pin-Out DiagramPackage outlines not drawn to scale.

Altera Corporation 61MAX 7000 Programmable Logic Device Family Data SheetFigure 18. 84-Pin Package Pin-Out DiagramPackage outline not drawn to scale.

62 Altera CorporationMAX 7000 Programmable Logic Device Family Data SheetFigure 19. 100-Pin Package Pin-Out DiagramPackage outline not drawn to scale.

Altera Corporation 63MAX 7000 Programmable Logic Device Family Data SheetFigure 21. 192-Pin Package Pin-Out DiagramPackage outline not drawn to scale

64 Altera CorporationMAX 7000 Programmable Logic Device Family Data SheetRevision HistoryThe information contained in the MAX 7000 Programmable Logic

Notes:Altera Corporation 65

Copyright © 2003 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, thestylized Altera logo, specific device designa

Altera Corporation 7MAX 7000 Programmable Logic Device Family Data SheetThe MAX 7000 architecture includes four dedicated inputs that can be used as

8 Altera CorporationMAX 7000 Programmable Logic Device Family Data SheetFigure2 shows the architecture of MAX 7000E and MAX 7000S devices.Figure 2. MA

Altera Corporation 9MAX 7000 Programmable Logic Device Family Data SheetEach LAB is fed by the following signals: 36 signals from the PIA that are u