Cadence M7000 Instrukcja Użytkownika Pobierz pdf (Strona 7)

Altera Corporation 7

MAX 7000 Programmable Logic Device Family Data Sheet

The MAX 7000 architecture includes four dedicated inputs that can

be used as general-purpose inputs or as high-speed, global control

signals (clock, clear, and two output enable signals) for each

macrocell and I/O pin. Figure 1 shows the architecture of EPM7032,

EPM7064, and EPM7096 devices.

Figure 1. EPM7032, EPM7064 & EPM7096 Device Block Diagram

I/O

Control

Block

8 to 16

I/O pins

8 to 16

I/O

Control

Block

8 to 16

I/O pins

8 to 16

I/O pins

8 to 16

I/O

Control

Block

I/O

Control

Block

8 to 16

I/O pins

8 to 16

LAB A LAB B

LAB C

Macrocells

33 to 48

LAB D

INPUT/GCLRn

INPUT/OE1

INPUT/OE2

Macrocells

17 to 32

Macrocells

49 to 64

PIA

INPUT/GLCK1

Macrocells

1 to 16

1 2 3 4 5 6 7 8 9 10 11 12 ... 65 66

MAX 7000 1
...and More 2
Features 2
General 3
Description 3
Functional 6
Altera Corporation 7 7
Logic Array Blocks 8
Macrocells 9
Programmable 10
Register 10
Fast Input 10
Expander Product Terms 11
Shareable Expanders 12
Parallel Expanders 12
I/O Control Blocks 14
Programma 16
In-System 16
Programming Sequence 17
Programming Times 18
Speed/Power 20
Configuration 20
Programming with 21
External Hardware 21
IEEE Std 22
1149.1 (JTAG) 22
Boundary-Scan 22
Operating 26
Conditions 26
Timing Model 28
Altera Corporation 29 29
Combinatorial Mode 30
Global Clock Mode 30
Array Clock Mode 30
Min Max Min Max 31
MAX 7000E (-10) 33
MAX 7000E (-12) 35
-15 -15T -20 37
Min Max Min Max Min Max 37
-15 -15T -20 38
-5 -6 -7 -10 39
-6 -7 -10 -15 44
MinMaxMinMaxMinMaxMinMax 44
-7 -10 -15 50
MinMaxMinMaxMinMax 51
Consumption 53
MAX7000 devices 55
Figure 14. I 55
Figure 15. I 57
Pin-Outs 58
44-Pin PLCC 59
44-Pin PQFP 59
44-Pin TQFP 59
68-Pin PLCC 60
84-Pin PLCC 61
100-Pin PQFP 62
100-Pin TQFP 62
160-Pin PGA 160-Pin PQFP 62
192-Pin PGA 63
208-Pin PQFP/RQFP 63
EPM7256E 63
EPM7256S 63
Revision 64
Altera Corporation 65 65

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